The present invention relates to a manufacturing method of a semiconductor device, more specifically, the present invention is applied to a MOSFET having a gate electrode of a polymetal structure wherein the refractory metal and polysilicon are stuck.
Conventionally, a MOSFET having a gate electrode of a polymetal structure (for example, W/WxNySiz/Si) wherein the refractory metal and polysilicon are stuck is manufactured by the following manufacturing process.
At first, a well-known technique is used so that a N type or P type well area is formed in a silicon substrate, and an element separation insulating film, which is composed of LOCOS or STI structure, is formed on the silicon substrate.
As shown in FIG. 1, a silicon oxide film (gate insulating film) 101 having a thicknes of about 4 nm is formed on the silicon substrate 100 as an element area surrounded by the element separation insulating film by thermal oxidation. Moreover, a polysilicon film 102 having a thickness of about 100 nm is formed on the silicon oxide film 101 by the CVD method. Thereafter, a donor such as phosphorus (P) is introduced into the polysilicon film 102 in the area where N-channel type MOSFET is formed, and an acceptor such as boron (B) is introduced into the polysilicon film 102 in the area where P-channel type MOSFET is formed by using the ion implantation method.
Next, as shown in FIG. 2, tungsten nitride film 103 having a thickness of about 5 nm, a tungsten film 104 having a thickness of about 40 nm and a silicon nitride film 105 having a thickness of about 180 nm are deposited on the polysilicon film 102 by using the CVD method or the sputter method so that a laminated film which is composed of silicon nitride film/tungsten film/tungsten nitride film/polysilicon film is formed.
Next, as shown in FIG. 3, a resist pattern (not shown) is formed on the silicon nitride film 105 by photo-lithography, and the silicon nitride film 105 is etched according to RIE by using the resist pattern as a mask. Thereafter, the resist pattern is removed.
Next, as shown in FIG. 4, the tungsten film 104, the tungsten nitride film 103 and the polysilicon film 102 are etched according to RIE by using the silicon nitride film 105 as a mask so that a gate electrode having a polymetal structure is formed.
Thereafter, a partial pressure of hydrogen and vapor (H.sub.2 O) is controlled so that only the silicon is selectively oxidized at a temperature of about 800.degree. C. without oxidizing the tungsten. As a result, a silicon oxide film 106 of about 3 nm (generally called a "post-oxide film", as it is an oxide film which is formed by the oxidizing process executed after processing the gate electrode) is formed selectively on exposed side surfaces of the silicon substrate 100 and the polysilicon film 102.
Here, the selective oxidation is used for forming the silicon oxide film 106 because if the tungsten film 104 is oxidized, abrupt volume expansion (abnormal oxidation) occurs, and thus the tungsten film 104 is broken.
Next, as shown in FIG. 5, impurity is implanted into the silicon substrate 100 according to the ion implantation method by using the gate electrode as a mask with the impurity being self-aligned. Here, an N type impurity such as phosphorus (P) is implanted as the impurity into the area where the N-channel type MOSFET is formed, and P type impurity such as boron (B) is implanted as the impurity into the area where the P-channel type MOSFET is formed. As a result, a shallow impurity area (hereinafter, referred to as extension area 108) is formed in the silicon substrate 100.
Thereafter, a silicon nitride film 107 having a thickness of about 20 nm which covers completely the gate electrode is deposited on the whole surface of the silicon substrate 100 by using the CVD method.
Next, as shown in FIG. 6, the silicon nitride film 107 is etched by RIE, and it is allowed to remain only on the side surface of the gate electrode, more concretely, on the side surfaces of the silicon nitride film 105, tungsten film 104, tungsten nitride film 103 and the polysilicon film 102. The silicon nitride film 107 on the side surface of the gate electrode is called a side wall.
In RIE, the silicon substrate 100 is used as an etching stopper. This is because since the silicon oxide film 106 is thin, and it cannot be used as the etching stopper (this point will be detailed below).
Thereafter, impurity is implanted into the silicon substrate 100 according to the ion implantation method by using the gate electrode and the side wall as a mask with the impurity being self-aligned. N type impurity such as phosphorus (P) and arsenic (As) is implanted as the impurity into the area where the N-channel type MOSFET is formed, and P type impurity such as boron (B) is implanted as the impurity into the area where the P-channel type MOSFET is formed. As a result, a source/drain area 109 which is denser and deeper than the extension area 108 is formed in the silicon substrate 100.
According to the above sequential process, the MOSFET having the gate electrode of the polymetal structure is finished.
(1) A disadvantage of the above-mentioned manufacturing process is that the silicon substrate 100 is used as the etching stopper in RIE of the silicon nitride film 107 for forming the side wall. In this RIE, the condition of the silicon substrate 100 is such that its etching is more difficult than the etching of the silicon nitride film 107, namely, such that the silicon substrate has an etching selective ratio with respect to the silicon nitride film 107. However, as shown in FIG. 7, the silicon substrate 100 is etched at the time of over-etching, and thus the silicon substrate 100 is occasionally damaged. Such damage causes an increase in junction leak current in the source/drain area 109.
(2) In addition, at the time of forming the side wall, the silicon substrate 100 is not used as the etching stopper, but the silicon oxide film 106 can be used as the etching stopper. However, as mentioned above, a thickness of the silicon oxide film 106 is set to several nm, namely, very thin. Moreover, in RIE of the silicon nitride film 107, the etching selective ratio of the silicon oxide film 106 and the silicon nitride film 107 cannot be large enough. Therefore, at the time of RIE, a hole is formed in the silicon oxide film 106, and further the silicon oxide film 106 is removed completely, and thus the silicon substrate 100 is exposed. As a result, the silicon substrate 100 does not have the etching selective ratio at all with respect to the silicon nitride film 107, and thus as shown in FIG. 8, the silicon substrate 100 is etched deep (OVER ETCH).
(3) In addition, the silicon oxide film 106 having a sufficient thickness can be formed by the selective oxidization after the process of the gate electrode. For example, the temperature of the selective oxidation is set to about 900.degree. C., and the thickness of the silicon oxide film 106 which is formed on the side surfaces of the silicon substrate 100 and the polysilicon film 102 can be set to about 60 nm. In this case, at the time of forming the side wall, if the silicon oxide film 106 is used as the etching stopper of RIE, the silicon oxide film 106 is not removed completely, and thus the etching of the silicon substrate 100 can be prevented.
However, in order to form the sufficiently thick silicon oxide film 106, the oxidation should be executed in an atmosphere of hydrogen which is higher than usual. In this case, as shown in FIG. 9, in the P-channel type MOSFET, the boron in the polysilicon film (gate electrode) 102 penetrates the silicon oxide film (gate insulating film) 101 so as to be diffused into the silicon substrate (channel) 100. Moreover, gate bird's beak is formed at the edge portion of the polysilicon film 102, and an effective gate insulating film is made to be thick. When such a situation arises, element properties such as the threshold value of MOSFET is scattered.